nv50_zcull_sources  106 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x07, "pc01_zcull_00", nv50_zcull_sources },
nv50_zcull_sources  107 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x08, "pc01_zcull_01", nv50_zcull_sources },
nv50_zcull_sources  108 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x09, "pc01_zcull_02", nv50_zcull_sources },
nv50_zcull_sources  109 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x0a, "pc01_zcull_03", nv50_zcull_sources },
nv50_zcull_sources  110 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x0b, "pc01_zcull_04", nv50_zcull_sources },
nv50_zcull_sources  111 drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c 			{ 0x0c, "pc01_zcull_05", nv50_zcull_sources },
nv50_zcull_sources   97 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x07, "pc01_zcull_00", nv50_zcull_sources },
nv50_zcull_sources   98 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x08, "pc01_zcull_01", nv50_zcull_sources },
nv50_zcull_sources   99 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x09, "pc01_zcull_02", nv50_zcull_sources },
nv50_zcull_sources  100 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x0a, "pc01_zcull_03", nv50_zcull_sources },
nv50_zcull_sources  101 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x0b, "pc01_zcull_04", nv50_zcull_sources },
nv50_zcull_sources  102 drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 			{ 0x0c, "pc01_zcull_05", nv50_zcull_sources },
nv50_zcull_sources   27 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c nv50_zcull_sources[] = {
nv50_zcull_sources  125 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x20, "pc01_zcull_00", nv50_zcull_sources },
nv50_zcull_sources  126 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x21, "pc01_zcull_01", nv50_zcull_sources },
nv50_zcull_sources  127 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x22, "pc01_zcull_02", nv50_zcull_sources },
nv50_zcull_sources  128 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x23, "pc01_zcull_03", nv50_zcull_sources },
nv50_zcull_sources  129 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x24, "pc01_zcull_04", nv50_zcull_sources },
nv50_zcull_sources  130 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c 			{ 0x25, "pc01_zcull_05", nv50_zcull_sources },
nv50_zcull_sources   46 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h extern const struct nvkm_specsrc nv50_zcull_sources[];