number_of_underlay_surfaces  208 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 	DC_LOG_BANDWIDTH_CALCS("	[uint32_t] number_of_underlay_surfaces: %d", data->number_of_underlay_surfaces);
number_of_underlay_surfaces  165 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->number_of_underlay_surfaces = d0_underlay_enable + d1_underlay_enable;
number_of_underlay_surfaces  497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
number_of_underlay_surfaces  964 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0) {
number_of_underlay_surfaces  257 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t number_of_underlay_surfaces;