number_of_underlay_pipes   54 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 	DC_LOG_BANDWIDTH_CALCS("	[uint32_t] number_of_underlay_pipes: %d", dceip->number_of_underlay_pipes);
number_of_underlay_pipes  497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
number_of_underlay_pipes 2088 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 1;
number_of_underlay_pipes 2204 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 0;
number_of_underlay_pipes 2320 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 0;
number_of_underlay_pipes 2436 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 0;
number_of_underlay_pipes 2549 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 1;
number_of_underlay_pipes 2662 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_underlay_pipes = 0;
number_of_underlay_pipes  146 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t number_of_underlay_pipes;