number_of_graphics_pipes   53 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 	DC_LOG_BANDWIDTH_CALCS("	[uint32_t] number_of_graphics_pipes: %d", dceip->number_of_graphics_pipes);
number_of_graphics_pipes  497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
number_of_graphics_pipes 2087 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 3;
number_of_graphics_pipes 2203 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 6;
number_of_graphics_pipes 2319 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 5;
number_of_graphics_pipes 2435 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 5;
number_of_graphics_pipes 2548 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 2;
number_of_graphics_pipes 2661 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		dceip.number_of_graphics_pipes = 6;
number_of_graphics_pipes  145 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t number_of_graphics_pipes;