number_of_displays  191 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 	DC_LOG_BANDWIDTH_CALCS("	[uint32_t] number_of_displays: %d", data->number_of_displays);
number_of_displays  292 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (i < data->number_of_displays + 4) {
number_of_displays  497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
number_of_displays  902 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					if (data->number_of_displays == 1) {
number_of_displays  911 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					if (data->number_of_displays == 1) {
number_of_displays  954 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma && dceip->limit_excessive_outstanding_dmif_requests && (data->number_of_displays > 1 || bw_mtn(data->total_requests_for_dmif_size, dceip->dmif_request_buffer_size))) {
number_of_displays  964 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0) {
number_of_displays  986 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {
number_of_displays 1889 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (data->number_of_displays > 1) {
number_of_displays 2978 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->number_of_displays = num_displays;
number_of_displays 3033 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	if (data->number_of_displays != 0) {
number_of_displays  239 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t number_of_displays;