num_wm_mcif_sets  556 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
num_wm_mcif_sets  574 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
num_wm_mcif_sets  678 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
num_wm_mcif_sets  696 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
num_wm_mcif_sets  175 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	uint32_t num_wm_mcif_sets;
num_wm_mcif_sets  713 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4)
num_wm_mcif_sets  737 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
num_wm_mcif_sets 1304 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	    clock_ranges->num_wm_mcif_sets > 4)
num_wm_mcif_sets 1328 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
num_wm_mcif_sets 3072 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    clock_ranges->num_wm_mcif_sets > 4)
num_wm_mcif_sets 3096 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {