num_states        513 arch/powerpc/kernel/rtas-proc.c 	int num_states = 0;
num_states        522 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(key_switch) / sizeof(char *);
num_states        523 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        530 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(enclosure_switch) / sizeof(char *);
num_states        531 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        543 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(lid_status) / sizeof(char *);
num_states        544 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        551 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(power_source) / sizeof(char *);
num_states        552 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        563 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(battery_remaining) / sizeof(char *);
num_states        564 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states)
num_states        576 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(epow_sensor) / sizeof(char *);
num_states        577 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        584 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(battery_cyclestate) / 
num_states        586 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        594 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(battery_charging) / sizeof(char *);
num_states        595 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states        612 arch/powerpc/kernel/rtas-proc.c 			num_states = sizeof(ibm_drconnector) / sizeof(char *);
num_states        613 arch/powerpc/kernel/rtas-proc.c 			if (state < num_states) {
num_states         78 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h 	uint32_t num_states;
num_states        886 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		unsigned int *clock_values_in_khz, unsigned int *num_states)
num_states        899 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			clock_values_in_khz, num_states))
num_states        231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	.num_states = 5,
num_states        342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	.num_states = 5,
num_states       2464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (vlevel <= context->bw_ctx.dml.soc.num_states)
num_states       2467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			vlevel = context->bw_ctx.dml.soc.num_states + 1;
num_states       2471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
num_states       2474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (vlevel > context->bw_ctx.dml.soc.num_states)
num_states       2520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
num_states       2570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
num_states       2610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
num_states       2877 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
num_states       3099 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < bb->num_states; i++) {
num_states       3134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = bb->num_states - 1; i > 1; i--) {
num_states       3155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			bb->num_states--;
num_states       3160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
num_states       3167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (num_states == 0)
num_states       3179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < num_states; i++) {
num_states       3210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	bb->num_states = num_calculated_states;
num_states       3214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	bb->clock_limits[num_calculated_states].state = bb->num_states;
num_states       3368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dcn2_0_nv12_soc.num_states =
num_states       3369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				le32_to_cpu(bb->num_states);
num_states       3371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
num_states       3396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		unsigned int num_states = 0;
num_states       3403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
num_states       3418 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (clock_limits_available && uclk_states_available && num_states)
num_states       3419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
num_states       3576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (loaded_bb->num_states == 1) {
num_states       3584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		} else if (loaded_bb->num_states > 1) {
num_states       3585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
num_states        266 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	.num_states = 5
num_states        958 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	ASSERT(vlevel < dml->soc.num_states);
num_states       1101 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
num_states       1283 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn2_1_soc.num_states = 0;
num_states       1293 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		dcn2_1_soc.num_states++;
num_states        236 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 			unsigned int *clock_values_in_khz, unsigned int *num_states);
num_states       1259 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
num_states       2596 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
num_states       3438 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3520 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3871 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 						&& i == mode_lib->vba.soc.num_states)
num_states       3893 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 						&& i == mode_lib->vba.soc.num_states)
num_states       3961 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 					if (i != mode_lib->vba.soc.num_states) {
num_states       3993 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4010 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4042 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4160 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4171 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4204 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4224 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4291 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4386 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4400 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       5007 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
num_states       5065 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
num_states       5066 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
num_states       1318 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
num_states       2628 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
num_states       3470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3552 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 						&& i == mode_lib->vba.soc.num_states)
num_states       3925 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 						&& i == mode_lib->vba.soc.num_states)
num_states       3993 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 					if (i != mode_lib->vba.soc.num_states) {
num_states       4025 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4042 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4074 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4192 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4236 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4256 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4323 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4418 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4437 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= locals->soc.num_states; i++) {
num_states       4951 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4963 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       5038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
num_states       5096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
num_states       5097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
num_states       1638 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
num_states       3542 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3584 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3938 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       3958 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 						&& i == mode_lib->vba.soc.num_states)
num_states       3965 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 						&& i == mode_lib->vba.soc.num_states)
num_states       4033 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 					if (i != mode_lib->vba.soc.num_states) {
num_states       4065 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4082 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4114 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4239 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4250 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4283 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4303 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       4370 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
num_states       4389 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       5019 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
num_states       5039 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states       5103 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
num_states       5162 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
num_states       5163 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
num_states        110 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int num_states;
num_states        235 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 	for (i = 0; i < mode_lib->vba.soc.num_states; i++)
num_states        253 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
num_states        457 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
num_states        755 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
num_states        756 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
num_states       1427 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
num_states       1435 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
num_states       1445 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	*num_states = num_discrete_levels;
num_states        421 include/net/ip_vs.h 	u16			num_states;
num_states        119 net/netfilter/ipvs/ip_vs_proto_ah_esp.c 	.num_states =		1,
num_states        141 net/netfilter/ipvs/ip_vs_proto_ah_esp.c 	.num_states =		1,
num_states        577 net/netfilter/ipvs/ip_vs_proto_sctp.c 	.num_states	= IP_VS_SCTP_S_LAST,
num_states        726 net/netfilter/ipvs/ip_vs_proto_tcp.c 	.num_states =		IP_VS_TCP_S_LAST,
num_states        485 net/netfilter/ipvs/ip_vs_proto_udp.c 	.num_states =		IP_VS_UDP_S_LAST,
num_states       1004 net/netfilter/ipvs/ip_vs_sync.c 			if (state >= pp->num_states) {
num_states       1163 net/netfilter/ipvs/ip_vs_sync.c 		if (state >= pp->num_states) {