num_slices_v     1880 drivers/gpu/drm/amd/display/dc/core/dc.c 				       update->dsc_config->num_slices_v != 0);
num_slices_v      114 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	stream->timing.dsc_cfg.num_slices_v = 0;
num_slices_v      767 drivers/gpu/drm/amd/display/dc/dc_hw_types.h 	uint32_t num_slices_v; /* Number of DSC slices - vertical */
num_slices_v      179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
num_slices_v      314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
num_slices_v      325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
num_slices_v      343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
num_slices_v      355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
num_slices_v      357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
num_slices_v      358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
num_slices_v      359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
num_slices_v      541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
num_slices_v      546 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	uint32_t num_slices_v;
num_slices_v      695 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_cfg->num_slices_v = pic_height/slice_height;