num_slices_h 1879 drivers/gpu/drm/amd/display/dc/core/dc.c uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && num_slices_h 404 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); num_slices_h 405 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; num_slices_h 415 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; num_slices_h 113 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.num_slices_h = 0; num_slices_h 766 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t num_slices_h; /* Number of DSC slices - horizontal */ num_slices_h 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); num_slices_h 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); num_slices_h 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || num_slices_h 342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; num_slices_h 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; num_slices_h 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; num_slices_h 539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, num_slices_h 545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h uint32_t num_slices_h; num_slices_h 1908 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; num_slices_h 2279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; num_slices_h 520 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c int num_slices_h; num_slices_h 651 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = min_slices_h; num_slices_h 654 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = min(dsc_policy.max_slices_h, max_slices_h); num_slices_h 656 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = max_slices_h; num_slices_h 662 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = min(dsc_policy.max_slices_h, max_slices_h); num_slices_h 664 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = max_slices_h; num_slices_h 666 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c num_slices_h = min_slices_h; num_slices_h 674 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->num_slices_h = num_slices_h; num_slices_h 675 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c slice_width = pic_width / num_slices_h;