num_secondary_tile_mode_states 1027 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c const u32 num_secondary_tile_mode_states = num_secondary_tile_mode_states 1050 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 1217 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 1400 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 1570 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2129 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); num_secondary_tile_mode_states 2138 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2308 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2498 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2687 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2890 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 3092 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 3263 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 3440 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2339 drivers/gpu/drm/radeon/cik.c const u32 num_secondary_tile_mode_states = num_secondary_tile_mode_states 2365 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2508 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2651 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 2876 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) num_secondary_tile_mode_states 3019 drivers/gpu/drm/radeon/cik.c for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)