num_opp           496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.num_opp = 4,
num_opp           506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.num_opp = 3,
num_opp           216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
num_opp           221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
num_opp          2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
num_opp           884 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.num_opp = 6,
num_opp           923 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.num_opp = 5,
num_opp          1360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
num_opp          1541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
num_opp          3661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
num_opp           728 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_opp = 4,
num_opp           743 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_opp = 4,
num_opp           755 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_opp = 2,
num_opp           888 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
num_opp          1591 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
num_opp            42 drivers/gpu/drm/amd/display/dc/inc/resource.h 	int num_opp;