num_dsc 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c for (i = 0; i < pool->res_cap->num_dsc; i++) { num_dsc 1258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c for (i = 0; i < res_pool->res_cap->num_dsc; i++) num_dsc 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .num_dsc = 6, num_dsc 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .num_dsc = 0, num_dsc 893 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .num_dsc = 6, num_dsc 1316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { num_dsc 1541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { num_dsc 1548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->res_cap->num_dsc; i++) num_dsc 1562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->res_cap->num_dsc; i++) num_dsc 3698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { num_dsc 94 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_dsc = 3, num_dsc 96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_dsc = 0, num_dsc 736 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_dsc = 3, num_dsc 750 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_dsc = 0, num_dsc 763 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_dsc = 2, num_dsc 844 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { num_dsc 1628 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { num_dsc 125 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int num_dsc; num_dsc 328 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.NumberOfDSC = ip->num_dsc; num_dsc 52 drivers/gpu/drm/amd/display/dc/inc/resource.h int num_dsc;