num_ddc           394 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		if (line < pool->res_cap->num_ddc)
num_ddc           366 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	.num_ddc = 6,
num_ddc           707 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1045 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           371 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		.num_ddc = 3,
num_ddc           380 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		.num_ddc = 3,
num_ddc           764 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1403 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           376 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		.num_ddc = 6,
num_ddc           384 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		.num_ddc = 5,
num_ddc           726 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1292 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           455 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		.num_ddc = 6,
num_ddc           577 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1144 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           359 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		.num_ddc = 6,
num_ddc           367 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		.num_ddc = 6,
num_ddc           375 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		.num_ddc = 2,
num_ddc           755 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1008 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1205 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1398 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           501 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.num_ddc = 4,
num_ddc           511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		.num_ddc = 4,
num_ddc           931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1497 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           890 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.num_ddc = 6,
num_ddc           929 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		.num_ddc = 5,
num_ddc          1347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          3643 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc           734 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_ddc = 5,
num_ddc           749 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_ddc = 4,
num_ddc           761 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		.num_ddc = 4,
num_ddc           875 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc          1573 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
num_ddc            48 drivers/gpu/drm/amd/display/dc/inc/resource.h 	int num_ddc;