num_clk 34 drivers/gpu/drm/exynos/exynos_drm_scaler.c unsigned int num_clk; num_clk 517 drivers/gpu/drm/exynos/exynos_drm_scaler.c for (i = 0; i < scaler->scaler_data->num_clk; ++i) { num_clk 569 drivers/gpu/drm/exynos/exynos_drm_scaler.c for (i = 0; i < scaler->scaler_data->num_clk; ++i) num_clk 705 drivers/gpu/drm/exynos/exynos_drm_scaler.c .num_clk = 1, num_clk 712 drivers/gpu/drm/exynos/exynos_drm_scaler.c .num_clk = 3, num_clk 16 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk) num_clk 20 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = num_clk - 1; i >= 0; i--) { num_clk 27 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk) num_clk 31 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = 0; i < num_clk; i++) { num_clk 54 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk) num_clk 58 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = 0; i < num_clk; i++) { num_clk 87 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) num_clk 92 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = 0; i < num_clk; i++) { num_clk 117 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = num_clk - 1; i >= 0; i--) { num_clk 139 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c int num_clk = 0; num_clk 144 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c mp->num_clk = 0; num_clk 145 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c num_clk = of_property_count_strings(pdev->dev.of_node, "clock-names"); num_clk 146 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c if (num_clk <= 0) { num_clk 152 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c num_clk, sizeof(struct dss_clk), num_clk 157 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = 0; i < num_clk; i++) { num_clk 172 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, num_clk); num_clk 184 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c for (i = 0; i < num_clk; i++) { num_clk 192 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c mp->num_clk = num_clk; num_clk 196 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c msm_dss_put_clk(mp->clk_config, num_clk); num_clk 30 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h unsigned int num_clk; num_clk 34 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk); num_clk 35 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); num_clk 36 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk); num_clk 37 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); num_clk 773 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c for (i = 0; i < mp->num_clk; i++) { num_clk 1034 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c msm_dss_put_clk(mp->clk_config, mp->num_clk); num_clk 1036 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c mp->num_clk = 0; num_clk 1072 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); num_clk 1094 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); num_clk 180 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); num_clk 193 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); num_clk 217 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c msm_dss_put_clk(mp->clk_config, mp->num_clk); num_clk 298 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c msm_dss_put_clk(mp->clk_config, mp->num_clk);