num_banks 202 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS; num_banks 115 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS; num_banks 212 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS; num_banks 115 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS; num_banks 190 drivers/crypto/qat/qat_common/adf_accel_devices.h uint8_t num_banks; num_banks 207 drivers/crypto/qat/qat_common/adf_accel_devices.h #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks) num_banks 408 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.banks_per_accel = hw_data->num_banks num_banks 72 drivers/crypto/qat/qat_common/adf_isr.c msix_num_entries += hw_data->num_banks; num_banks 77 drivers/crypto/qat/qat_common/adf_isr.c hw_data->num_banks; num_banks 174 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { num_banks 190 drivers/crypto/qat/qat_common/adf_isr.c cpu = ((accel_dev->accel_id * hw_data->num_banks) + num_banks 220 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { num_banks 239 drivers/crypto/qat/qat_common/adf_isr.c msix_num_entries += hw_data->num_banks; num_banks 285 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) num_banks 298 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { num_banks 465 drivers/crypto/qat/qat_common/adf_transport.c uint32_t num_banks = 0; num_banks 473 drivers/crypto/qat/qat_common/adf_transport.c num_banks = GET_MAX_BANKS(accel_dev); num_banks 474 drivers/crypto/qat/qat_common/adf_transport.c size = num_banks * sizeof(struct adf_etr_bank_data); num_banks 490 drivers/crypto/qat/qat_common/adf_transport.c for (i = 0; i < num_banks; i++) { num_banks 531 drivers/crypto/qat/qat_common/adf_transport.c uint32_t i, num_banks = GET_MAX_BANKS(accel_dev); num_banks 533 drivers/crypto/qat/qat_common/adf_transport.c for (i = 0; i < num_banks; i++) num_banks 225 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS; num_banks 115 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->num_banks = ADF_DH895XCCIOV_ETR_MAX_BANKS; num_banks 298 drivers/edac/qcom_edac.c for (i = 0; i < drv->num_banks; i++) { num_banks 349 drivers/edac/qcom_edac.c llcc_driv_data->num_banks, 1, num_banks 373 drivers/gpio/gpio-brcmstb.c int num_banks = num_banks 376 drivers/gpio/gpio-brcmstb.c if (res_num_banks != num_banks) { num_banks 378 drivers/gpio/gpio-brcmstb.c res_num_banks, num_banks); num_banks 616 drivers/gpio/gpio-brcmstb.c int num_banks = 0; num_banks 671 drivers/gpio/gpio-brcmstb.c num_banks); num_banks 672 drivers/gpio/gpio-brcmstb.c num_banks++; num_banks 684 drivers/gpio/gpio-brcmstb.c bank->id = num_banks; num_banks 743 drivers/gpio/gpio-brcmstb.c num_banks++; num_banks 179 drivers/gpio/gpio-stmpe.c int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); num_banks 210 drivers/gpio/gpio-stmpe.c for (j = 0; j < num_banks; j++) { num_banks 373 drivers/gpio/gpio-stmpe.c int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); num_banks 391 drivers/gpio/gpio-stmpe.c ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); num_banks 395 drivers/gpio/gpio-stmpe.c for (i = 0; i < num_banks; i++) { num_banks 397 drivers/gpio/gpio-stmpe.c num_banks - i - 1; num_banks 125 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, num_banks 157 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, num_banks 112 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, num_banks 121 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h uint8_t num_banks; num_banks 68 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h uint32_t num_banks; num_banks 1971 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c unsigned bankw, bankh, mtaspect, tile_split, num_banks; num_banks 1977 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); num_banks 1979 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); num_banks 2013 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c unsigned bankw, bankh, mtaspect, tile_split, num_banks; num_banks 2019 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); num_banks 2021 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); num_banks 1918 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c unsigned bankw, bankh, mtaspect, tile_split, num_banks; num_banks 1924 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); num_banks 1926 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c fb_format |= GRPH_NUM_BANKS(num_banks); num_banks 1892 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c unsigned bankw, bankh, mtaspect, tile_split, num_banks; num_banks 1898 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); num_banks 1900 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); num_banks 1943 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev->gfx.config.gb_addr_config_fields.num_banks = 1 << num_banks 1157 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c args->num_banks = config.num_banks; num_banks 1204 drivers/gpu/drm/amd/amdkfd/kfd_crat.c cu->num_banks = cu_info.num_shader_engines; num_banks 110 drivers/gpu/drm/amd/amdkfd/kfd_crat.h uint8_t num_banks; num_banks 2825 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c unsigned int bankw, bankh, mtaspect, tile_split, num_banks; num_banks 2831 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); num_banks 2834 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.num_banks = num_banks; num_banks 2866 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_banks = num_banks 2867 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c adev->gfx.config.gb_addr_config_fields.num_banks; num_banks 142 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.num_banks, num_banks 234 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.num_banks, num_banks 323 drivers/gpu/drm/amd/display/dc/dc_hw_types.h unsigned int num_banks; num_banks 385 drivers/gpu/drm/amd/display/dc/dc_hw_types.h unsigned int num_banks; num_banks 361 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), num_banks 374 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_NUM_BANKS, info->gfx8.num_banks, num_banks 171 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c set_reg_field_value(value, info->gfx8.num_banks, num_banks 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c NUM_BANKS, log_2(info->gfx9.num_banks), num_banks 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .num_banks = 8, num_banks 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .num_banks = 8, num_banks 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .num_banks = 8, num_banks 3346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn2_0_nv12_soc.num_banks = num_banks 3347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c le32_to_cpu(bb->num_banks); num_banks 257 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .num_banks = 8, num_banks 98 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int num_banks; num_banks 163 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t num_banks; num_banks 1281 drivers/gpu/drm/radeon/atombios_crtc.c unsigned index, num_banks; num_banks 1301 drivers/gpu/drm/radeon/atombios_crtc.c num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; num_banks 1316 drivers/gpu/drm/radeon/atombios_crtc.c num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; num_banks 1319 drivers/gpu/drm/radeon/atombios_crtc.c fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); num_banks 440 drivers/memory/emif.c if (addressing->num_banks == B8) num_banks 477 drivers/memory/emif.c if (addressing->num_banks == B8) { num_banks 116 drivers/memory/jedec_ddr.h u32 num_banks; num_banks 50 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c unsigned int num_banks; num_banks 409 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c if (num_chips > nfc->num_banks) { num_banks 411 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c num_chips, nfc->num_banks); num_banks 432 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c unsigned int num_banks; num_banks 436 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c num_banks = jz4780_nemc_num_banks(dev); num_banks 437 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c if (num_banks == 0) { num_banks 442 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL); num_banks 459 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c nfc->num_banks = num_banks; num_banks 1600 drivers/net/wireless/ath/ath10k/htt.h u8 num_banks; num_banks 1609 drivers/net/wireless/ath/ath10k/htt.h u8 num_banks; num_banks 663 drivers/net/wireless/ath/ath10k/htt_tx.c cfg->num_banks = 1; num_banks 725 drivers/net/wireless/ath/ath10k/htt_tx.c cfg->num_banks = 1; num_banks 111 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned num_banks; num_banks 173 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c for (i = 0; i < chip->num_banks; i++) { num_banks 831 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; num_banks 1052 drivers/pinctrl/meson/pinctrl-meson-axg.c .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), num_banks 1066 drivers/pinctrl/meson/pinctrl-meson-axg.c .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), num_banks 1374 drivers/pinctrl/meson/pinctrl-meson-g12a.c .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), num_banks 1388 drivers/pinctrl/meson/pinctrl-meson-g12a.c .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), num_banks 839 drivers/pinctrl/meson/pinctrl-meson-gxbb.c .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), num_banks 852 drivers/pinctrl/meson/pinctrl-meson-gxbb.c .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), num_banks 808 drivers/pinctrl/meson/pinctrl-meson-gxl.c .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), num_banks 821 drivers/pinctrl/meson/pinctrl-meson-gxl.c .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), num_banks 73 drivers/pinctrl/meson/pinctrl-meson.c for (i = 0; i < pc->data->num_banks; i++) { num_banks 114 drivers/pinctrl/meson/pinctrl-meson.h unsigned int num_banks; num_banks 1091 drivers/pinctrl/meson/pinctrl-meson8.c .num_banks = ARRAY_SIZE(meson8_cbus_banks), num_banks 1104 drivers/pinctrl/meson/pinctrl-meson8.c .num_banks = ARRAY_SIZE(meson8_aobus_banks), num_banks 950 drivers/pinctrl/meson/pinctrl-meson8b.c .num_banks = ARRAY_SIZE(meson8b_cbus_banks), num_banks 963 drivers/pinctrl/meson/pinctrl-meson8b.c .num_banks = ARRAY_SIZE(meson8b_aobus_banks), num_banks 281 drivers/soc/qcom/llcc-slice.c max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; num_banks 333 drivers/soc/qcom/llcc-slice.c u32 num_banks; num_banks 358 drivers/soc/qcom/llcc-slice.c &num_banks); num_banks 362 drivers/soc/qcom/llcc-slice.c num_banks &= LLCC_LB_CNT_MASK; num_banks 363 drivers/soc/qcom/llcc-slice.c num_banks >>= LLCC_LB_CNT_SHIFT; num_banks 364 drivers/soc/qcom/llcc-slice.c drv_data->num_banks = num_banks; num_banks 370 drivers/soc/qcom/llcc-slice.c drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), num_banks 377 drivers/soc/qcom/llcc-slice.c for (i = 0; i < num_banks; i++) num_banks 236 drivers/thermal/mtk_thermal.c s32 num_banks; num_banks 376 drivers/thermal/mtk_thermal.c .num_banks = MT8173_NUM_ZONES, num_banks 415 drivers/thermal/mtk_thermal.c .num_banks = 1, num_banks 445 drivers/thermal/mtk_thermal.c .num_banks = 1, num_banks 469 drivers/thermal/mtk_thermal.c .num_banks = MT7622_NUM_ZONES, num_banks 501 drivers/thermal/mtk_thermal.c .num_banks = MT8183_NUM_SENSORS_PER_ZONE, num_banks 622 drivers/thermal/mtk_thermal.c for (i = 0; i < mt->conf->num_banks; i++) { num_banks 948 drivers/thermal/mtk_thermal.c for (i = 0; i < mt->conf->num_banks; i++) num_banks 90 include/linux/soc/qcom/llcc-qcom.h u32 num_banks; num_banks 318 include/uapi/linux/kfd_ioctl.h __u32 num_banks; /* from KFD */