nrirqs             76 drivers/irqchip/irq-dw-apb-ictl.c 	int ret, nrirqs, irq, i;
nrirqs            119 drivers/irqchip/irq-dw-apb-ictl.c 		nrirqs = 32 + fls(reg);
nrirqs            121 drivers/irqchip/irq-dw-apb-ictl.c 		nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
nrirqs            123 drivers/irqchip/irq-dw-apb-ictl.c 	domain = irq_domain_add_linear(np, nrirqs,
nrirqs            139 drivers/irqchip/irq-dw-apb-ictl.c 	for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) {
nrirqs            145 drivers/irqchip/irq-orion.c 	int ret, irq, nrirqs = 32;
nrirqs            148 drivers/irqchip/irq-orion.c 	of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
nrirqs            150 drivers/irqchip/irq-orion.c 	domain = irq_domain_add_linear(np, nrirqs,
nrirqs            157 drivers/irqchip/irq-orion.c 	ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
nrirqs             99 drivers/irqchip/irq-tb10x.c 	int i, ret, nrirqs = of_irq_count(ictl);
nrirqs            162 drivers/irqchip/irq-tb10x.c 	for (i = 0; i < nrirqs; i++) {
nrirqs           2030 drivers/nvme/host/pci.c static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
nrirqs           2046 drivers/nvme/host/pci.c 	if (!nrirqs) {
nrirqs           2047 drivers/nvme/host/pci.c 		nrirqs = 1;
nrirqs           2049 drivers/nvme/host/pci.c 	} else if (nrirqs == 1 || !write_queues) {
nrirqs           2051 drivers/nvme/host/pci.c 	} else if (write_queues >= nrirqs) {
nrirqs           2054 drivers/nvme/host/pci.c 		nr_read_queues = nrirqs - write_queues;
nrirqs           2057 drivers/nvme/host/pci.c 	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
nrirqs           2058 drivers/nvme/host/pci.c 	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;