OUTPUT_CSC_CONTROL 2162 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
OUTPUT_CSC_CONTROL 2163 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
OUTPUT_CSC_CONTROL 2196 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
OUTPUT_CSC_CONTROL 1004 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1009 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1016 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 				REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1021 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 				REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1027 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 				REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1033 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 				REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1044 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1050 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1056 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1062 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL 1071 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_SET(OUTPUT_CSC_CONTROL, 0,
OUTPUT_CSC_CONTROL   53 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
OUTPUT_CSC_CONTROL  146 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
OUTPUT_CSC_CONTROL  400 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t OUTPUT_CSC_CONTROL;