nlw               188 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h 		__BITFIELD_FIELD(uint32_t nlw:6,
nlw               656 arch/mips/pci/pcie-octeon.c 	switch (pciercx_cfg032.s.nlw) {
nlw              1075 arch/mips/pci/pcie-octeon.c 	cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
nlw              1119 arch/mips/pci/pcie-octeon.c 	switch (pciercx_cfg032.s.nlw) {
nlw              1430 arch/mips/pci/pcie-octeon.c 	pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);