OTG_V_TOTAL_CONTROL  858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_CONTROL  871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_CONTROL  882 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_CONTROL 1313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_CONTROL 1316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_CONTROL   59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
OTG_V_TOTAL_CONTROL  131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t OTG_V_TOTAL_CONTROL;