OTG_V_TOTAL       203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_SET(OTG_V_TOTAL, 0,
OTG_V_TOTAL       204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			OTG_V_TOTAL, v_total);
OTG_V_TOTAL      1304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_V_TOTAL,
OTG_V_TOTAL      1305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			OTG_V_TOTAL, &s->v_total);
OTG_V_TOTAL      1525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
OTG_V_TOTAL        47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL, OTG, inst),\
OTG_V_TOTAL       119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t OTG_V_TOTAL;
OTG_V_TOTAL       197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
OTG_V_TOTAL       335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	type OTG_V_TOTAL;\
OTG_V_TOTAL       479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;