OTG_TEST_PATTERN_CONTROL  959 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
OTG_TEST_PATTERN_CONTROL 1059 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
OTG_TEST_PATTERN_CONTROL 1133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
OTG_TEST_PATTERN_CONTROL 1135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
OTG_TEST_PATTERN_CONTROL 1144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
OTG_TEST_PATTERN_CONTROL   96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
OTG_TEST_PATTERN_CONTROL  143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t OTG_TEST_PATTERN_CONTROL;