OTG_STEREO_CONTROL 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_STEREO_CONTROL, 0, OTG_STEREO_CONTROL 1185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_UPDATE_3(OTG_STEREO_CONTROL, OTG_STEREO_CONTROL 1191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_UPDATE(OTG_STEREO_CONTROL, OTG_STEREO_CONTROL 1196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_UPDATE(OTG_STEREO_CONTROL, OTG_STEREO_CONTROL 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STEREO_CONTROL, OTG, inst),\ OTG_STEREO_CONTROL 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_STEREO_CONTROL;