OTG_MASTER_UPDATE_LOCK 598 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK 599 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_MASTER_UPDATE_LOCK, 1); OTG_MASTER_UPDATE_LOCK 604 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_WAIT(OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK 614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_MASTER_UPDATE_LOCK, 0); OTG_MASTER_UPDATE_LOCK 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ OTG_MASTER_UPDATE_LOCK 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_MASTER_UPDATE_LOCK; OTG_MASTER_UPDATE_LOCK 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ OTG_MASTER_UPDATE_LOCK 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h type OTG_MASTER_UPDATE_LOCK;\ OTG_MASTER_UPDATE_LOCK 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OTG_MASTER_UPDATE_LOCK, 1); OTG_MASTER_UPDATE_LOCK 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_WAIT(OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK 340 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OTG_MASTER_UPDATE_LOCK, 0);