OTG_H_TOTAL 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_SET(OTG_H_TOTAL, 0, OTG_H_TOTAL 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_H_TOTAL, patched_crtc_timing.h_total - 1); OTG_H_TOTAL 1334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_H_TOTAL, OTG_H_TOTAL 1335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_H_TOTAL, &s->h_total); OTG_H_TOTAL 1524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; OTG_H_TOTAL 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_TOTAL, OTG, inst),\ OTG_H_TOTAL 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h uint32_t OTG_H_TOTAL; OTG_H_TOTAL 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ OTG_H_TOTAL 328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h type OTG_H_TOTAL;\ OTG_H_TOTAL 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;