OTG_H_TIMING_CNTL  291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_CNTL   46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
OTG_H_TIMING_CNTL  118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t OTG_H_TIMING_CNTL;
OTG_H_TIMING_CNTL  222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_WRITE(OTG_H_TIMING_CNTL, 0);
OTG_H_TIMING_CNTL  225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_CNTL  277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);