OTG_CONTROL       265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE_2(OTG_CONTROL,
OTG_CONTROL       461 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE_2(OTG_CONTROL,
OTG_CONTROL       476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_UPDATE_2(OTG_CONTROL,
OTG_CONTROL       590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	regval = REG_READ(OTG_CONTROL);
OTG_CONTROL      1294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_CONTROL,
OTG_CONTROL      1353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_CONTROL,
OTG_CONTROL      1390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
OTG_CONTROL        52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CONTROL, OTG, inst),\
OTG_CONTROL       124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t OTG_CONTROL;
OTG_CONTROL        63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_UPDATE_2(OTG_CONTROL,