OTG0_OTG_V_TOTAL_CONTROL  221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
OTG0_OTG_V_TOTAL_CONTROL  227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\