nfe               278 drivers/crypto/hisilicon/qm.c 	void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
nfe               981 drivers/crypto/hisilicon/qm.c static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
nfe               990 drivers/crypto/hisilicon/qm.c static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
nfe               993 drivers/crypto/hisilicon/qm.c 	u32 irq_enable = ce | nfe | fe | msi;
nfe               996 drivers/crypto/hisilicon/qm.c 	qm->error_mask = ce | nfe | fe;
nfe              1002 drivers/crypto/hisilicon/qm.c 	writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
nfe              1861 drivers/crypto/hisilicon/qm.c void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
nfe              1870 drivers/crypto/hisilicon/qm.c 	qm->ops->hw_error_init(qm, ce, nfe, fe, msi);
nfe               210 drivers/crypto/hisilicon/qm.h void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,