OSSSYS_BASE 44 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 45 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 45 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 45 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 47 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 46 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); OSSSYS_BASE 119 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, OSSSYS_BASE 103 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, OSSSYS_BASE 137 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, OSSSYS_BASE 137 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, OSSSYS_BASE 172 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, OSSSYS_BASE 163 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, OSSSYS_BASE 105 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },