OSSSYS            279 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
OSSSYS            183 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
OSSSYS            200 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,
OSSSYS            419 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
OSSSYS            421 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
OSSSYS            621 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
OSSSYS            623 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
OSSSYS             47 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS             51 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS             64 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS             68 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS             70 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
OSSSYS             71 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
OSSSYS            123 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
OSSSYS            124 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
OSSSYS            126 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS            133 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
OSSSYS            136 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
OSSSYS            140 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS            143 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
OSSSYS            145 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
OSSSYS            149 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
OSSSYS            150 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
OSSSYS            152 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
OSSSYS            163 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
OSSSYS            168 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
OSSSYS            171 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
OSSSYS            173 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
OSSSYS            175 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
OSSSYS            220 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
OSSSYS            236 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS            302 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
OSSSYS            405 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 		def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
OSSSYS            418 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
OSSSYS            444 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
OSSSYS             49 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS             59 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS             64 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
OSSSYS             74 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
OSSSYS             80 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
OSSSYS             90 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
OSSSYS            105 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS            115 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS            119 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
OSSSYS            120 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
OSSSYS            125 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
OSSSYS            135 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
OSSSYS            138 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
OSSSYS            139 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
OSSSYS            145 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
OSSSYS            155 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
OSSSYS            159 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
OSSSYS            160 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
OSSSYS            233 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
OSSSYS            234 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
OSSSYS            236 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS            237 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
OSSSYS            253 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
OSSSYS            259 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
OSSSYS            262 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
OSSSYS            264 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
OSSSYS            268 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
OSSSYS            269 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
OSSSYS            271 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
OSSSYS            276 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);
OSSSYS            277 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
OSSSYS            280 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
OSSSYS            293 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
OSSSYS            297 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
OSSSYS            298 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
OSSSYS            300 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,
OSSSYS            306 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);
OSSSYS            307 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
OSSSYS            310 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
OSSSYS            320 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
OSSSYS            324 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
OSSSYS            325 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
OSSSYS            327 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,
OSSSYS            331 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
OSSSYS            334 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
OSSSYS            336 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
OSSSYS            338 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
OSSSYS            386 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
OSSSYS            388 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
OSSSYS            390 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
OSSSYS            411 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
OSSSYS            413 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
OSSSYS            415 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
OSSSYS            484 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
OSSSYS            486 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
OSSSYS            488 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
OSSSYS            520 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
OSSSYS            522 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);
OSSSYS            524 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);