new_clocks 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) new_clocks 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; new_clocks 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; new_clocks 46 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; new_clocks 53 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 58 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (new_clocks->dispclk_khz <= disp_clk_threshold) new_clocks 59 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 63 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 72 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 78 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 82 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c return new_clocks->dispclk_khz; new_clocks 88 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clocks *new_clocks) new_clocks 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); new_clocks 92 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; new_clocks 114 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz) { new_clocks 115 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz); new_clocks 120 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; new_clocks 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; new_clocks 122 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; new_clocks 132 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; new_clocks 159 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz new_clocks 160 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz new_clocks 161 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz new_clocks 162 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) new_clocks 165 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { new_clocks 166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; new_clocks 172 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c new_clocks->fclk_khz = debug->force_fclk_khz; new_clocks 174 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { new_clocks 175 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; new_clocks 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { new_clocks 181 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; new_clocks 186 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { new_clocks 187 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; new_clocks 199 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); new_clocks 200 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); new_clocks 201 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); new_clocks 207 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) new_clocks 208 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c || new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) { new_clocks 209 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks); new_clocks 210 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; new_clocks 219 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); new_clocks 220 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); new_clocks 221 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); new_clocks 191 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; new_clocks 222 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { new_clocks 223 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; new_clocks 230 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? new_clocks 231 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); new_clocks 233 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { new_clocks 234 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; new_clocks 240 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { new_clocks 241 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; new_clocks 246 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { new_clocks 247 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; new_clocks 252 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { new_clocks 255 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; new_clocks 261 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { new_clocks 262 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; new_clocks 269 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) new_clocks 270 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz); new_clocks 277 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz) new_clocks 278 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); new_clocks 295 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz) new_clocks 296 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz); new_clocks 325 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; new_clocks 327 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; new_clocks 329 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { new_clocks 330 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; new_clocks 333 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { new_clocks 334 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; new_clocks 338 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { new_clocks 339 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; new_clocks 342 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { new_clocks 343 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; new_clocks 346 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { new_clocks 347 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; new_clocks 350 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { new_clocks 351 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; new_clocks 358 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { new_clocks 359 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; new_clocks 60 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; new_clocks 78 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { new_clocks 79 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; new_clocks 83 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { new_clocks 84 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; new_clocks 89 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { new_clocks 90 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; new_clocks 96 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (new_clocks->dppclk_khz < 100000) new_clocks 97 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c new_clocks->dppclk_khz = 100000; new_clocks 100 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { new_clocks 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) new_clocks 103 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; new_clocks 107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { new_clocks 108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; new_clocks 357 sound/isa/es18xx.c static const struct snd_ratnum new_clocks[2] = { new_clocks 374 sound/isa/es18xx.c .rats = new_clocks, new_clocks 405 sound/isa/es18xx.c if (runtime->rate_num == new_clocks[0].num)