OBUF_MEM_PWR_CTRL   83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(OBUF_MEM_PWR_CTRL,
OBUF_MEM_PWR_CTRL  166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
OBUF_MEM_PWR_CTRL  619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	uint32_t OBUF_MEM_PWR_CTRL;\