ndfc 45 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(nchip); ndfc 47 drivers/mtd/nand/raw/ndfc.c ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); ndfc 50 drivers/mtd/nand/raw/ndfc.c ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); ndfc 53 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); ndfc 58 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 64 drivers/mtd/nand/raw/ndfc.c writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); ndfc 66 drivers/mtd/nand/raw/ndfc.c writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); ndfc 71 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 73 drivers/mtd/nand/raw/ndfc.c return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; ndfc 79 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 81 drivers/mtd/nand/raw/ndfc.c ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); ndfc 83 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); ndfc 90 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 95 drivers/mtd/nand/raw/ndfc.c ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); ndfc 113 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 117 drivers/mtd/nand/raw/ndfc.c *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); ndfc 122 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = nand_get_controller_data(chip); ndfc 126 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); ndfc 132 drivers/mtd/nand/raw/ndfc.c static int ndfc_chip_init(struct ndfc_controller *ndfc, ndfc 136 drivers/mtd/nand/raw/ndfc.c struct nand_chip *chip = &ndfc->chip; ndfc 140 drivers/mtd/nand/raw/ndfc.c chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; ndfc 141 drivers/mtd/nand/raw/ndfc.c chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; ndfc 146 drivers/mtd/nand/raw/ndfc.c chip->controller = &ndfc->ndfc_control; ndfc 156 drivers/mtd/nand/raw/ndfc.c nand_set_controller_data(chip, ndfc); ndfc 158 drivers/mtd/nand/raw/ndfc.c mtd->dev.parent = &ndfc->ofdev->dev; ndfc 165 drivers/mtd/nand/raw/ndfc.c mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev), ndfc 187 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc; ndfc 206 drivers/mtd/nand/raw/ndfc.c ndfc = &ndfc_ctrl[cs]; ndfc 207 drivers/mtd/nand/raw/ndfc.c ndfc->chip_select = cs; ndfc 209 drivers/mtd/nand/raw/ndfc.c nand_controller_init(&ndfc->ndfc_control); ndfc 210 drivers/mtd/nand/raw/ndfc.c ndfc->ofdev = ofdev; ndfc 211 drivers/mtd/nand/raw/ndfc.c dev_set_drvdata(&ofdev->dev, ndfc); ndfc 213 drivers/mtd/nand/raw/ndfc.c ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); ndfc 214 drivers/mtd/nand/raw/ndfc.c if (!ndfc->ndfcbase) { ndfc 219 drivers/mtd/nand/raw/ndfc.c ccr = NDFC_CCR_BS(ndfc->chip_select); ndfc 226 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); ndfc 231 drivers/mtd/nand/raw/ndfc.c int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); ndfc 232 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); ndfc 235 drivers/mtd/nand/raw/ndfc.c err = ndfc_chip_init(ndfc, ofdev->dev.of_node); ndfc 237 drivers/mtd/nand/raw/ndfc.c iounmap(ndfc->ndfcbase); ndfc 246 drivers/mtd/nand/raw/ndfc.c struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); ndfc 247 drivers/mtd/nand/raw/ndfc.c struct mtd_info *mtd = nand_to_mtd(&ndfc->chip); ndfc 249 drivers/mtd/nand/raw/ndfc.c nand_release(&ndfc->chip);