BrateCfg         1256 drivers/staging/rtl8188eu/hal/usb_halinit.c 			u16 BrateCfg = 0;
BrateCfg         1263 drivers/staging/rtl8188eu/hal/usb_halinit.c 			hal_set_brate_cfg(val, &BrateCfg);
BrateCfg         1264 drivers/staging/rtl8188eu/hal/usb_halinit.c 			DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
BrateCfg         1271 drivers/staging/rtl8188eu/hal/usb_halinit.c 			BrateCfg = (BrateCfg | 0xd) & 0x15d;
BrateCfg         1272 drivers/staging/rtl8188eu/hal/usb_halinit.c 			haldata->BasicRateSet = BrateCfg;
BrateCfg         1274 drivers/staging/rtl8188eu/hal/usb_halinit.c 			BrateCfg |= 0x01; /*  default enable 1M ACK rate */
BrateCfg         1276 drivers/staging/rtl8188eu/hal/usb_halinit.c 			usb_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
BrateCfg         1277 drivers/staging/rtl8188eu/hal/usb_halinit.c 			usb_write8(Adapter, REG_RRSR + 1, (BrateCfg >> 8) & 0xff);
BrateCfg         1281 drivers/staging/rtl8188eu/hal/usb_halinit.c 			while (BrateCfg > 0x1) {
BrateCfg         1282 drivers/staging/rtl8188eu/hal/usb_halinit.c 				BrateCfg >>= 1;
BrateCfg         3813 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
BrateCfg         3817 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		HalSetBrateCfg(padapter, val, &BrateCfg);
BrateCfg         3818 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		input_b = BrateCfg;
BrateCfg         3821 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		BrateCfg |= rrsr_2g_force_mask;
BrateCfg         3822 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		BrateCfg &= rrsr_2g_allow_mask;
BrateCfg         3823 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		masked = BrateCfg;
BrateCfg         3826 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M); /* use 11M to send ACK */
BrateCfg         3827 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M); /* CMCC_OFDM_ACK 12/18/24M */
BrateCfg         3833 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 			if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
BrateCfg         3834 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 				BrateCfg |= RRSR_6M;
BrateCfg         3836 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		ioted = BrateCfg;
BrateCfg         3838 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		pHalData->BasicRateSet = BrateCfg;
BrateCfg         3843 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c 		rtw_write16(padapter, REG_RRSR, BrateCfg);