nandc 183 drivers/mtd/nand/raw/qcom_nandc.c #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ nandc 184 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \ nandc 193 drivers/mtd/nand/raw/qcom_nandc.c #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) nandc 471 drivers/mtd/nand/raw/qcom_nandc.c static void free_bam_transaction(struct qcom_nand_controller *nandc) nandc 473 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 475 drivers/mtd/nand/raw/qcom_nandc.c devm_kfree(nandc->dev, bam_txn); nandc 480 drivers/mtd/nand/raw/qcom_nandc.c alloc_bam_transaction(struct qcom_nand_controller *nandc) nandc 484 drivers/mtd/nand/raw/qcom_nandc.c unsigned int num_cw = nandc->max_cwperpage; nandc 493 drivers/mtd/nand/raw/qcom_nandc.c bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); nandc 516 drivers/mtd/nand/raw/qcom_nandc.c static void clear_bam_transaction(struct qcom_nand_controller *nandc) nandc 518 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 520 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->props->is_bam) nandc 534 drivers/mtd/nand/raw/qcom_nandc.c sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * nandc 536 drivers/mtd/nand/raw/qcom_nandc.c sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * nandc 572 drivers/mtd/nand/raw/qcom_nandc.c static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) nandc 574 drivers/mtd/nand/raw/qcom_nandc.c return ioread32(nandc->base + offset); nandc 577 drivers/mtd/nand/raw/qcom_nandc.c static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, nandc 580 drivers/mtd/nand/raw/qcom_nandc.c iowrite32(val, nandc->base + offset); nandc 583 drivers/mtd/nand/raw/qcom_nandc.c static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, nandc 586 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->props->is_bam) nandc 590 drivers/mtd/nand/raw/qcom_nandc.c dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, nandc 592 drivers/mtd/nand/raw/qcom_nandc.c sizeof(*nandc->reg_read_buf), nandc 595 drivers/mtd/nand/raw/qcom_nandc.c dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, nandc 597 drivers/mtd/nand/raw/qcom_nandc.c sizeof(*nandc->reg_read_buf), nandc 647 drivers/mtd/nand/raw/qcom_nandc.c static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, nandc 650 drivers/mtd/nand/raw/qcom_nandc.c struct nandc_regs *regs = nandc->regs; nandc 663 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 668 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); nandc 669 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); nandc 682 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 708 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CMD, cmd); nandc 709 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); nandc 710 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); nandc 711 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg); nandc 712 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); nandc 713 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); nandc 714 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); nandc 715 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EXEC_CMD, 1); nandc 718 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? nandc 727 drivers/mtd/nand/raw/qcom_nandc.c static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, nandc 735 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 743 drivers/mtd/nand/raw/qcom_nandc.c if (chan == nandc->cmd_chan) { nandc 749 drivers/mtd/nand/raw/qcom_nandc.c } else if (chan == nandc->tx_chan) { nandc 764 drivers/mtd/nand/raw/qcom_nandc.c ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); nandc 766 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure in mapping desc\n"); nandc 778 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure in prep desc\n"); nandc 779 drivers/mtd/nand/raw/qcom_nandc.c dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); nandc 787 drivers/mtd/nand/raw/qcom_nandc.c if (chan == nandc->cmd_chan) nandc 792 drivers/mtd/nand/raw/qcom_nandc.c list_add_tail(&desc->node, &nandc->desc_list); nandc 806 drivers/mtd/nand/raw/qcom_nandc.c static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, nandc 813 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 821 drivers/mtd/nand/raw/qcom_nandc.c nandc_reg_phys(nandc, reg_off + 4 * i), nandc 823 drivers/mtd/nand/raw/qcom_nandc.c reg_buf_dma_addr(nandc, nandc 827 drivers/mtd/nand/raw/qcom_nandc.c nandc_reg_phys(nandc, reg_off + 4 * i), nandc 846 drivers/mtd/nand/raw/qcom_nandc.c ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, nandc 861 drivers/mtd/nand/raw/qcom_nandc.c static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, nandc 866 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 882 drivers/mtd/nand/raw/qcom_nandc.c ret = prepare_bam_async_desc(nandc, nandc->tx_chan, nandc 892 drivers/mtd/nand/raw/qcom_nandc.c static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, nandc 919 drivers/mtd/nand/raw/qcom_nandc.c ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); nandc 930 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.src_addr = nandc->base_dma + reg_off; nandc 931 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.slave_id = nandc->data_crci; nandc 934 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.dst_addr = nandc->base_dma + reg_off; nandc 935 drivers/mtd/nand/raw/qcom_nandc.c slave_conf.slave_id = nandc->cmd_crci; nandc 938 drivers/mtd/nand/raw/qcom_nandc.c ret = dmaengine_slave_config(nandc->chan, &slave_conf); nandc 940 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to configure dma channel\n"); nandc 944 drivers/mtd/nand/raw/qcom_nandc.c dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); nandc 946 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to prepare desc\n"); nandc 953 drivers/mtd/nand/raw/qcom_nandc.c list_add_tail(&desc->node, &nandc->desc_list); nandc 970 drivers/mtd/nand/raw/qcom_nandc.c static int read_reg_dma(struct qcom_nand_controller *nandc, int first, nandc 976 drivers/mtd/nand/raw/qcom_nandc.c vaddr = nandc->reg_read_buf + nandc->reg_read_pos; nandc 977 drivers/mtd/nand/raw/qcom_nandc.c nandc->reg_read_pos += num_regs; nandc 980 drivers/mtd/nand/raw/qcom_nandc.c first = dev_cmd_reg_addr(nandc, first); nandc 982 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 983 drivers/mtd/nand/raw/qcom_nandc.c return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, nandc 989 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, true, first, vaddr, nandc 1001 drivers/mtd/nand/raw/qcom_nandc.c static int write_reg_dma(struct qcom_nand_controller *nandc, int first, nandc 1005 drivers/mtd/nand/raw/qcom_nandc.c struct nandc_regs *regs = nandc->regs; nandc 1021 drivers/mtd/nand/raw/qcom_nandc.c first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); nandc 1024 drivers/mtd/nand/raw/qcom_nandc.c first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); nandc 1026 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 1027 drivers/mtd/nand/raw/qcom_nandc.c return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, nandc 1033 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, false, first, vaddr, nandc 1046 drivers/mtd/nand/raw/qcom_nandc.c static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, nandc 1049 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 1050 drivers/mtd/nand/raw/qcom_nandc.c return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); nandc 1052 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); nandc 1064 drivers/mtd/nand/raw/qcom_nandc.c static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, nandc 1067 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 1068 drivers/mtd/nand/raw/qcom_nandc.c return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); nandc 1070 drivers/mtd/nand/raw/qcom_nandc.c return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); nandc 1077 drivers/mtd/nand/raw/qcom_nandc.c static void config_nand_page_read(struct qcom_nand_controller *nandc) nandc 1079 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_ADDR0, 2, 0); nandc 1080 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); nandc 1081 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); nandc 1082 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); nandc 1083 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, nandc 1092 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc) nandc 1094 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 1095 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, nandc 1098 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1099 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1102 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); nandc 1103 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, nandc 1106 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1115 drivers/mtd/nand/raw/qcom_nandc.c config_nand_single_cw_page_read(struct qcom_nand_controller *nandc, nandc 1118 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_read(nandc); nandc 1119 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_read(nandc, use_ecc); nandc 1126 drivers/mtd/nand/raw/qcom_nandc.c static void config_nand_page_write(struct qcom_nand_controller *nandc) nandc 1128 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_ADDR0, 2, 0); nandc 1129 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); nandc 1130 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, nandc 1138 drivers/mtd/nand/raw/qcom_nandc.c static void config_nand_cw_write(struct qcom_nand_controller *nandc) nandc 1140 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1141 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1143 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1145 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); nandc 1146 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1158 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1165 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE); nandc 1166 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR0, 0); nandc 1167 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR1, 0); nandc 1168 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE nandc 1172 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES nandc 1179 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); nandc 1182 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV_CMD_VLD, nandc 1183 drivers/mtd/nand/raw/qcom_nandc.c (nandc->vld & ~READ_START_VLD)); nandc 1184 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV_CMD1, nandc 1185 drivers/mtd/nand/raw/qcom_nandc.c (nandc->cmd1 & ~(0xFF << READ_ADDR)) nandc 1188 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EXEC_CMD, 1); nandc 1190 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); nandc 1191 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); nandc 1192 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, 0, 512, 1); nandc 1194 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); nandc 1195 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); nandc 1197 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_count = 512; nandc 1198 drivers/mtd/nand/raw/qcom_nandc.c memset(nandc->data_buffer, 0xff, nandc->buf_count); nandc 1200 drivers/mtd/nand/raw/qcom_nandc.c config_nand_single_cw_page_read(nandc, false); nandc 1202 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, nandc 1203 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_count, 0); nandc 1206 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); nandc 1207 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); nandc 1216 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1218 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CMD, nandc 1220 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR0, page_addr); nandc 1221 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR1, 0); nandc 1222 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG0, nandc 1224 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); nandc 1225 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EXEC_CMD, 1); nandc 1226 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); nandc 1227 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); nandc 1229 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); nandc 1230 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); nandc 1231 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1233 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1235 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); nandc 1236 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1245 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1250 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID); nandc 1251 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR0, column); nandc 1252 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_ADDR1, 0); nandc 1253 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, nandc 1254 drivers/mtd/nand/raw/qcom_nandc.c nandc->props->is_bam ? 0 : DM_EN); nandc 1255 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EXEC_CMD, 1); nandc 1257 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); nandc 1258 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1260 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); nandc 1269 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1271 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE); nandc 1272 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_EXEC_CMD, 1); nandc 1274 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1275 drivers/mtd/nand/raw/qcom_nandc.c write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); nandc 1277 drivers/mtd/nand/raw/qcom_nandc.c read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); nandc 1283 drivers/mtd/nand/raw/qcom_nandc.c static int submit_descs(struct qcom_nand_controller *nandc) nandc 1287 drivers/mtd/nand/raw/qcom_nandc.c struct bam_transaction *bam_txn = nandc->bam_txn; nandc 1290 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 1292 drivers/mtd/nand/raw/qcom_nandc.c r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); nandc 1298 drivers/mtd/nand/raw/qcom_nandc.c r = prepare_bam_async_desc(nandc, nandc->tx_chan, nandc 1305 drivers/mtd/nand/raw/qcom_nandc.c r = prepare_bam_async_desc(nandc, nandc->cmd_chan, nandc 1312 drivers/mtd/nand/raw/qcom_nandc.c list_for_each_entry(desc, &nandc->desc_list, node) nandc 1315 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 1324 drivers/mtd/nand/raw/qcom_nandc.c dma_async_issue_pending(nandc->tx_chan); nandc 1325 drivers/mtd/nand/raw/qcom_nandc.c dma_async_issue_pending(nandc->rx_chan); nandc 1326 drivers/mtd/nand/raw/qcom_nandc.c dma_async_issue_pending(nandc->cmd_chan); nandc 1332 drivers/mtd/nand/raw/qcom_nandc.c if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) nandc 1339 drivers/mtd/nand/raw/qcom_nandc.c static void free_descs(struct qcom_nand_controller *nandc) nandc 1343 drivers/mtd/nand/raw/qcom_nandc.c list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { nandc 1346 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) nandc 1347 drivers/mtd/nand/raw/qcom_nandc.c dma_unmap_sg(nandc->dev, desc->bam_sgl, nandc 1350 drivers/mtd/nand/raw/qcom_nandc.c dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, nandc 1358 drivers/mtd/nand/raw/qcom_nandc.c static void clear_read_regs(struct qcom_nand_controller *nandc) nandc 1360 drivers/mtd/nand/raw/qcom_nandc.c nandc->reg_read_pos = 0; nandc 1361 drivers/mtd/nand/raw/qcom_nandc.c nandc_read_buffer_sync(nandc, false); nandc 1367 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1369 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_count = 0; nandc 1370 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_start = 0; nandc 1374 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 1378 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 1389 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1395 drivers/mtd/nand/raw/qcom_nandc.c nandc_read_buffer_sync(nandc, true); nandc 1398 drivers/mtd/nand/raw/qcom_nandc.c u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); nandc 1413 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1417 drivers/mtd/nand/raw/qcom_nandc.c nandc_read_buffer_sync(nandc, true); nandc 1418 drivers/mtd/nand/raw/qcom_nandc.c memcpy(nandc->data_buffer, nandc->reg_read_buf, nandc 1419 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_count); nandc 1441 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1454 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_count = 4; nandc 1491 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure executing command %d\n", nandc 1493 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 1498 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 1500 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, nandc 1505 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 1568 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1572 drivers/mtd/nand/raw/qcom_nandc.c u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); nandc 1587 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1595 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 1598 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_read(nandc); nandc 1613 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 1614 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); nandc 1617 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); nandc 1620 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); nandc 1623 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); nandc 1626 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_read(nandc, false); nandc 1628 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, data_buf, data_size1, 0); nandc 1631 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); nandc 1634 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); nandc 1637 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); nandc 1639 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 1640 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 1642 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to read raw cw %d\n", cw); nandc 1728 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1737 drivers/mtd/nand/raw/qcom_nandc.c buf = (struct read_stats *)nandc->reg_read_buf; nandc 1738 drivers/mtd/nand/raw/qcom_nandc.c nandc_read_buffer_sync(nandc, true); nandc 1832 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1837 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_read(nandc); nandc 1852 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 1854 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, 0, data_size, 0); nandc 1855 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 1, data_size, nandc 1858 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, 0, data_size, 1); nandc 1860 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_read_loc(nandc, 0, data_size, nandc 1865 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_read(nandc, true); nandc 1868 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, FLASH_BUF_ACC, data_buf, nandc 1884 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, FLASH_BUF_ACC + data_size, nandc 1894 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 1895 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 1898 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to read page/oob\n"); nandc 1912 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1917 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 1922 drivers/mtd/nand/raw/qcom_nandc.c memset(nandc->data_buffer, 0xff, size); nandc 1927 drivers/mtd/nand/raw/qcom_nandc.c config_nand_single_cw_page_read(nandc, host->use_ecc); nandc 1929 drivers/mtd/nand/raw/qcom_nandc.c read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); nandc 1931 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 1933 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to copy last codeword\n"); nandc 1935 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 1945 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1952 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 1984 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 1987 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 1988 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2002 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2009 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 2010 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2017 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_write(nandc); nandc 2032 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, nandc 2045 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, FLASH_BUF_ACC + data_size, nandc 2049 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_write(nandc); nandc 2055 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 2057 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to write page\n"); nandc 2059 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 2074 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2080 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 2081 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2088 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_write(nandc); nandc 2107 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, data_buf, data_size1, nandc 2112 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, oob_buf, oob_size1, nandc 2117 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, data_buf, data_size2, nandc 2122 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); nandc 2125 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_write(nandc); nandc 2128 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 2130 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to write raw page\n"); nandc 2132 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 2151 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2158 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2164 drivers/mtd/nand/raw/qcom_nandc.c memset(nandc->data_buffer, 0xff, host->cw_data); nandc 2166 drivers/mtd/nand/raw/qcom_nandc.c mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, nandc 2172 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_write(nandc); nandc 2173 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, FLASH_BUF_ACC, nandc 2174 drivers/mtd/nand/raw/qcom_nandc.c nandc->data_buffer, data_size + oob_size, 0); nandc 2175 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_write(nandc); nandc 2177 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 2179 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 2182 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to write oob\n"); nandc 2193 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2207 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2213 drivers/mtd/nand/raw/qcom_nandc.c dev_warn(nandc->dev, "error when trying to read BBM\n"); nandc 2219 drivers/mtd/nand/raw/qcom_nandc.c bad = nandc->data_buffer[bbpos] != 0xff; nandc 2222 drivers/mtd/nand/raw/qcom_nandc.c bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); nandc 2230 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2234 drivers/mtd/nand/raw/qcom_nandc.c clear_read_regs(nandc); nandc 2235 drivers/mtd/nand/raw/qcom_nandc.c clear_bam_transaction(nandc); nandc 2242 drivers/mtd/nand/raw/qcom_nandc.c memset(nandc->data_buffer, 0x00, host->cw_size); nandc 2251 drivers/mtd/nand/raw/qcom_nandc.c config_nand_page_write(nandc); nandc 2252 drivers/mtd/nand/raw/qcom_nandc.c write_data_dma(nandc, FLASH_BUF_ACC, nandc 2253 drivers/mtd/nand/raw/qcom_nandc.c nandc->data_buffer, host->cw_size, 0); nandc 2254 drivers/mtd/nand/raw/qcom_nandc.c config_nand_cw_write(nandc); nandc 2256 drivers/mtd/nand/raw/qcom_nandc.c ret = submit_descs(nandc); nandc 2258 drivers/mtd/nand/raw/qcom_nandc.c free_descs(nandc); nandc 2261 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failure to update BBM\n"); nandc 2277 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2278 drivers/mtd/nand/raw/qcom_nandc.c u8 *buf = nandc->data_buffer; nandc 2289 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->buf_start < nandc->buf_count) nandc 2290 drivers/mtd/nand/raw/qcom_nandc.c ret = buf[nandc->buf_start++]; nandc 2297 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2298 drivers/mtd/nand/raw/qcom_nandc.c int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); nandc 2300 drivers/mtd/nand/raw/qcom_nandc.c memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); nandc 2301 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_start += real_len; nandc 2307 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2308 drivers/mtd/nand/raw/qcom_nandc.c int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); nandc 2310 drivers/mtd/nand/raw/qcom_nandc.c memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); nandc 2312 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_start += real_len; nandc 2318 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2323 drivers/mtd/nand/raw/qcom_nandc.c dev_warn(nandc->dev, "invalid chip select\n"); nandc 2467 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc 2484 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "No valid ECC settings possible\n"); nandc 2508 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->ecc_modes & ECC_BCH_4BIT) { nandc 2555 drivers/mtd/nand/raw/qcom_nandc.c nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, nandc 2613 drivers/mtd/nand/raw/qcom_nandc.c nandc->regs->erased_cw_detect_cfg_clr = nandc 2615 drivers/mtd/nand/raw/qcom_nandc.c nandc->regs->erased_cw_detect_cfg_set = nandc 2618 drivers/mtd/nand/raw/qcom_nandc.c dev_dbg(nandc->dev, nandc 2631 drivers/mtd/nand/raw/qcom_nandc.c static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) nandc 2635 drivers/mtd/nand/raw/qcom_nandc.c ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); nandc 2637 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to set DMA mask\n"); nandc 2647 drivers/mtd/nand/raw/qcom_nandc.c nandc->buf_size = 532; nandc 2649 drivers/mtd/nand/raw/qcom_nandc.c nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, nandc 2651 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->data_buffer) nandc 2654 drivers/mtd/nand/raw/qcom_nandc.c nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), nandc 2656 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->regs) nandc 2659 drivers/mtd/nand/raw/qcom_nandc.c nandc->reg_read_buf = devm_kcalloc(nandc->dev, nandc 2660 drivers/mtd/nand/raw/qcom_nandc.c MAX_REG_RD, sizeof(*nandc->reg_read_buf), nandc 2662 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->reg_read_buf) nandc 2665 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 2666 drivers/mtd/nand/raw/qcom_nandc.c nandc->reg_read_dma = nandc 2667 drivers/mtd/nand/raw/qcom_nandc.c dma_map_single(nandc->dev, nandc->reg_read_buf, nandc 2669 drivers/mtd/nand/raw/qcom_nandc.c sizeof(*nandc->reg_read_buf), nandc 2671 drivers/mtd/nand/raw/qcom_nandc.c if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { nandc 2672 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); nandc 2676 drivers/mtd/nand/raw/qcom_nandc.c nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx"); nandc 2677 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->tx_chan) { nandc 2678 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to request tx channel\n"); nandc 2682 drivers/mtd/nand/raw/qcom_nandc.c nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx"); nandc 2683 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->rx_chan) { nandc 2684 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to request rx channel\n"); nandc 2688 drivers/mtd/nand/raw/qcom_nandc.c nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd"); nandc 2689 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->cmd_chan) { nandc 2690 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "failed to request cmd channel\n"); nandc 2700 drivers/mtd/nand/raw/qcom_nandc.c nandc->max_cwperpage = 1; nandc 2701 drivers/mtd/nand/raw/qcom_nandc.c nandc->bam_txn = alloc_bam_transaction(nandc); nandc 2702 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->bam_txn) { nandc 2703 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, nandc 2708 drivers/mtd/nand/raw/qcom_nandc.c nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx"); nandc 2709 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->chan) { nandc 2710 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, nandc 2716 drivers/mtd/nand/raw/qcom_nandc.c INIT_LIST_HEAD(&nandc->desc_list); nandc 2717 drivers/mtd/nand/raw/qcom_nandc.c INIT_LIST_HEAD(&nandc->host_list); nandc 2719 drivers/mtd/nand/raw/qcom_nandc.c nand_controller_init(&nandc->controller); nandc 2720 drivers/mtd/nand/raw/qcom_nandc.c nandc->controller.ops = &qcom_nandc_ops; nandc 2725 drivers/mtd/nand/raw/qcom_nandc.c static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) nandc 2727 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 2728 drivers/mtd/nand/raw/qcom_nandc.c if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) nandc 2729 drivers/mtd/nand/raw/qcom_nandc.c dma_unmap_single(nandc->dev, nandc->reg_read_dma, nandc 2731 drivers/mtd/nand/raw/qcom_nandc.c sizeof(*nandc->reg_read_buf), nandc 2734 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->tx_chan) nandc 2735 drivers/mtd/nand/raw/qcom_nandc.c dma_release_channel(nandc->tx_chan); nandc 2737 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->rx_chan) nandc 2738 drivers/mtd/nand/raw/qcom_nandc.c dma_release_channel(nandc->rx_chan); nandc 2740 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->cmd_chan) nandc 2741 drivers/mtd/nand/raw/qcom_nandc.c dma_release_channel(nandc->cmd_chan); nandc 2743 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->chan) nandc 2744 drivers/mtd/nand/raw/qcom_nandc.c dma_release_channel(nandc->chan); nandc 2749 drivers/mtd/nand/raw/qcom_nandc.c static int qcom_nandc_setup(struct qcom_nand_controller *nandc) nandc 2754 drivers/mtd/nand/raw/qcom_nandc.c nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc 2755 drivers/mtd/nand/raw/qcom_nandc.c nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), nandc 2759 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 2760 drivers/mtd/nand/raw/qcom_nandc.c nand_ctrl = nandc_read(nandc, NAND_CTRL); nandc 2761 drivers/mtd/nand/raw/qcom_nandc.c nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); nandc 2763 drivers/mtd/nand/raw/qcom_nandc.c nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); nandc 2767 drivers/mtd/nand/raw/qcom_nandc.c nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); nandc 2768 drivers/mtd/nand/raw/qcom_nandc.c nandc->vld = NAND_DEV_CMD_VLD_VAL; nandc 2773 drivers/mtd/nand/raw/qcom_nandc.c static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, nandc 2779 drivers/mtd/nand/raw/qcom_nandc.c struct device *dev = nandc->dev; nandc 2815 drivers/mtd/nand/raw/qcom_nandc.c chip->controller = &nandc->controller; nandc 2826 drivers/mtd/nand/raw/qcom_nandc.c if (nandc->props->is_bam) { nandc 2827 drivers/mtd/nand/raw/qcom_nandc.c free_bam_transaction(nandc); nandc 2828 drivers/mtd/nand/raw/qcom_nandc.c nandc->bam_txn = alloc_bam_transaction(nandc); nandc 2829 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->bam_txn) { nandc 2830 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, nandc 2843 drivers/mtd/nand/raw/qcom_nandc.c static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) nandc 2845 drivers/mtd/nand/raw/qcom_nandc.c struct device *dev = nandc->dev; nandc 2857 drivers/mtd/nand/raw/qcom_nandc.c ret = qcom_nand_host_init_and_register(nandc, host, child); nandc 2863 drivers/mtd/nand/raw/qcom_nandc.c list_add_tail(&host->node, &nandc->host_list); nandc 2866 drivers/mtd/nand/raw/qcom_nandc.c if (list_empty(&nandc->host_list)) nandc 2875 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); nandc 2876 drivers/mtd/nand/raw/qcom_nandc.c struct device_node *np = nandc->dev->of_node; nandc 2879 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->props->is_bam) { nandc 2881 drivers/mtd/nand/raw/qcom_nandc.c &nandc->cmd_crci); nandc 2883 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "command CRCI unspecified\n"); nandc 2888 drivers/mtd/nand/raw/qcom_nandc.c &nandc->data_crci); nandc 2890 drivers/mtd/nand/raw/qcom_nandc.c dev_err(nandc->dev, "data CRCI unspecified\n"); nandc 2900 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc; nandc 2906 drivers/mtd/nand/raw/qcom_nandc.c nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); nandc 2907 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc) nandc 2910 drivers/mtd/nand/raw/qcom_nandc.c platform_set_drvdata(pdev, nandc); nandc 2911 drivers/mtd/nand/raw/qcom_nandc.c nandc->dev = dev; nandc 2919 drivers/mtd/nand/raw/qcom_nandc.c nandc->props = dev_data; nandc 2921 drivers/mtd/nand/raw/qcom_nandc.c nandc->core_clk = devm_clk_get(dev, "core"); nandc 2922 drivers/mtd/nand/raw/qcom_nandc.c if (IS_ERR(nandc->core_clk)) nandc 2923 drivers/mtd/nand/raw/qcom_nandc.c return PTR_ERR(nandc->core_clk); nandc 2925 drivers/mtd/nand/raw/qcom_nandc.c nandc->aon_clk = devm_clk_get(dev, "aon"); nandc 2926 drivers/mtd/nand/raw/qcom_nandc.c if (IS_ERR(nandc->aon_clk)) nandc 2927 drivers/mtd/nand/raw/qcom_nandc.c return PTR_ERR(nandc->aon_clk); nandc 2934 drivers/mtd/nand/raw/qcom_nandc.c nandc->base = devm_ioremap_resource(dev, res); nandc 2935 drivers/mtd/nand/raw/qcom_nandc.c if (IS_ERR(nandc->base)) nandc 2936 drivers/mtd/nand/raw/qcom_nandc.c return PTR_ERR(nandc->base); nandc 2938 drivers/mtd/nand/raw/qcom_nandc.c nandc->base_phys = res->start; nandc 2939 drivers/mtd/nand/raw/qcom_nandc.c nandc->base_dma = dma_map_resource(dev, res->start, nandc 2942 drivers/mtd/nand/raw/qcom_nandc.c if (!nandc->base_dma) nandc 2945 drivers/mtd/nand/raw/qcom_nandc.c ret = qcom_nandc_alloc(nandc); nandc 2949 drivers/mtd/nand/raw/qcom_nandc.c ret = clk_prepare_enable(nandc->core_clk); nandc 2953 drivers/mtd/nand/raw/qcom_nandc.c ret = clk_prepare_enable(nandc->aon_clk); nandc 2957 drivers/mtd/nand/raw/qcom_nandc.c ret = qcom_nandc_setup(nandc); nandc 2961 drivers/mtd/nand/raw/qcom_nandc.c ret = qcom_probe_nand_devices(nandc); nandc 2968 drivers/mtd/nand/raw/qcom_nandc.c clk_disable_unprepare(nandc->aon_clk); nandc 2970 drivers/mtd/nand/raw/qcom_nandc.c clk_disable_unprepare(nandc->core_clk); nandc 2972 drivers/mtd/nand/raw/qcom_nandc.c qcom_nandc_unalloc(nandc); nandc 2982 drivers/mtd/nand/raw/qcom_nandc.c struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); nandc 2986 drivers/mtd/nand/raw/qcom_nandc.c list_for_each_entry(host, &nandc->host_list, node) nandc 2990 drivers/mtd/nand/raw/qcom_nandc.c qcom_nandc_unalloc(nandc); nandc 2992 drivers/mtd/nand/raw/qcom_nandc.c clk_disable_unprepare(nandc->aon_clk); nandc 2993 drivers/mtd/nand/raw/qcom_nandc.c clk_disable_unprepare(nandc->core_clk); nandc 2995 drivers/mtd/nand/raw/qcom_nandc.c dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res),