n_io             3808 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3816 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3824 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3883 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3891 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3899 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;
n_io             3945 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;				/* RW */
n_io             3953 arch/x86/include/asm/uv/uv_mmrs.h 		unsigned long	n_io:4;				/* RW */
n_io              922 arch/x86/kernel/apic/x2apic_uv_x.c 	int shift, enable, m_io, n_io;
n_io              938 arch/x86/kernel/apic/x2apic_uv_x.c 		n_io	= mmioh.s1.n_io;
n_io              946 arch/x86/kernel/apic/x2apic_uv_x.c 		n_io	= mmioh.s2.n_io;
n_io              952 arch/x86/kernel/apic/x2apic_uv_x.c 		max_pnode &= (1 << n_io) - 1;
n_io              953 arch/x86/kernel/apic/x2apic_uv_x.c 		pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);