n_IRQ             129 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
n_IRQ             282 arch/powerpc/kvm/mpic.c static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ)
n_IRQ             284 arch/powerpc/kvm/mpic.c 	set_bit(n_IRQ, q->queue);
n_IRQ             287 arch/powerpc/kvm/mpic.c static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ)
n_IRQ             289 arch/powerpc/kvm/mpic.c 	clear_bit(n_IRQ, q->queue);
n_IRQ             324 arch/powerpc/kvm/mpic.c static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,
n_IRQ             332 arch/powerpc/kvm/mpic.c 	src = &opp->src[n_IRQ];
n_IRQ             335 arch/powerpc/kvm/mpic.c 		__func__, n_IRQ, active, was_active);
n_IRQ             339 arch/powerpc/kvm/mpic.c 			__func__, src->output, n_IRQ, active, was_active,
n_IRQ             350 arch/powerpc/kvm/mpic.c 					__func__, src->output, n_CPU, n_IRQ);
n_IRQ             357 arch/powerpc/kvm/mpic.c 					__func__, src->output, n_CPU, n_IRQ);
n_IRQ             371 arch/powerpc/kvm/mpic.c 		IRQ_setbit(&dst->raised, n_IRQ);
n_IRQ             373 arch/powerpc/kvm/mpic.c 		IRQ_resetbit(&dst->raised, n_IRQ);
n_IRQ             379 arch/powerpc/kvm/mpic.c 			__func__, n_IRQ, priority, dst->ctpr, n_CPU);
n_IRQ             387 arch/powerpc/kvm/mpic.c 				__func__, n_IRQ, dst->servicing.next, n_CPU);
n_IRQ             390 arch/powerpc/kvm/mpic.c 				__func__, n_CPU, n_IRQ, dst->raised.next);
n_IRQ             398 arch/powerpc/kvm/mpic.c 				__func__, n_IRQ, dst->raised.next,
n_IRQ             404 arch/powerpc/kvm/mpic.c 				__func__, n_IRQ, dst->ctpr,
n_IRQ             412 arch/powerpc/kvm/mpic.c static void openpic_update_irq(struct openpic *opp, int n_IRQ)
n_IRQ             418 arch/powerpc/kvm/mpic.c 	src = &opp->src[n_IRQ];
n_IRQ             423 arch/powerpc/kvm/mpic.c 		pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ);
n_IRQ             434 arch/powerpc/kvm/mpic.c 		pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
n_IRQ             445 arch/powerpc/kvm/mpic.c 		pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ);
n_IRQ             451 arch/powerpc/kvm/mpic.c 		IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
n_IRQ             456 arch/powerpc/kvm/mpic.c 				IRQ_local_pipe(opp, i, n_IRQ, active,
n_IRQ             467 arch/powerpc/kvm/mpic.c 				IRQ_local_pipe(opp, i, n_IRQ, active,
n_IRQ             476 arch/powerpc/kvm/mpic.c static void openpic_set_irq(void *opaque, int n_IRQ, int level)
n_IRQ             481 arch/powerpc/kvm/mpic.c 	if (n_IRQ >= MAX_IRQ) {
n_IRQ             482 arch/powerpc/kvm/mpic.c 		WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ);
n_IRQ             486 arch/powerpc/kvm/mpic.c 	src = &opp->src[n_IRQ];
n_IRQ             488 arch/powerpc/kvm/mpic.c 		n_IRQ, level, src->ivpr);
n_IRQ             492 arch/powerpc/kvm/mpic.c 		openpic_update_irq(opp, n_IRQ);
n_IRQ             497 arch/powerpc/kvm/mpic.c 			openpic_update_irq(opp, n_IRQ);
n_IRQ             508 arch/powerpc/kvm/mpic.c 			openpic_update_irq(opp, n_IRQ);
n_IRQ             562 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)
n_IRQ             564 arch/powerpc/kvm/mpic.c 	return opp->src[n_IRQ].idr;
n_IRQ             567 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)
n_IRQ             570 arch/powerpc/kvm/mpic.c 		return opp->src[n_IRQ].output;
n_IRQ             575 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)
n_IRQ             577 arch/powerpc/kvm/mpic.c 	return opp->src[n_IRQ].ivpr;
n_IRQ             580 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
n_IRQ             583 arch/powerpc/kvm/mpic.c 	struct irq_source *src = &opp->src[n_IRQ];
n_IRQ             596 arch/powerpc/kvm/mpic.c 	pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
n_IRQ             625 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,
n_IRQ             629 arch/powerpc/kvm/mpic.c 		struct irq_source *src = &opp->src[n_IRQ];
n_IRQ             632 arch/powerpc/kvm/mpic.c 		pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
n_IRQ             639 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,
n_IRQ             651 arch/powerpc/kvm/mpic.c 	opp->src[n_IRQ].ivpr =
n_IRQ             652 arch/powerpc/kvm/mpic.c 	    (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
n_IRQ             658 arch/powerpc/kvm/mpic.c 	switch (opp->src[n_IRQ].type) {
n_IRQ             660 arch/powerpc/kvm/mpic.c 		opp->src[n_IRQ].level =
n_IRQ             661 arch/powerpc/kvm/mpic.c 		    !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
n_IRQ             665 arch/powerpc/kvm/mpic.c 		opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
n_IRQ             669 arch/powerpc/kvm/mpic.c 		opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
n_IRQ             673 arch/powerpc/kvm/mpic.c 	openpic_update_irq(opp, n_IRQ);
n_IRQ             674 arch/powerpc/kvm/mpic.c 	pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
n_IRQ             675 arch/powerpc/kvm/mpic.c 		opp->src[n_IRQ].ivpr);
n_IRQ            1030 arch/powerpc/kvm/mpic.c 	int s_IRQ, n_IRQ;
n_IRQ            1096 arch/powerpc/kvm/mpic.c 		n_IRQ = IRQ_get_next(opp, &dst->raised);
n_IRQ            1097 arch/powerpc/kvm/mpic.c 		src = &opp->src[n_IRQ];
n_IRQ            1098 arch/powerpc/kvm/mpic.c 		if (n_IRQ != -1 &&
n_IRQ            1102 arch/powerpc/kvm/mpic.c 				idx, n_IRQ);