mvdd_table        653 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			&data->dpm_table.mvdd_table,
mvdd_table        745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
mvdd_table        746 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
mvdd_table        748 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
mvdd_table        109 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	struct smu7_single_dpm_table  mvdd_table;
mvdd_table       3476 drivers/gpu/drm/radeon/ci_dpm.c 				  &pi->dpm_table.mvdd_table,
mvdd_table       3527 drivers/gpu/drm/radeon/ci_dpm.c 			pi->dpm_table.mvdd_table.dpm_levels[i].value =
mvdd_table       3529 drivers/gpu/drm/radeon/ci_dpm.c 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
mvdd_table       3531 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
mvdd_table         74 drivers/gpu/drm/radeon/ci_dpm.h 	struct ci_single_dpm_table mvdd_table;