mvdd_dependency_on_mclk  367 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
mvdd_dependency_on_mclk  726 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 	kfree(dyn_state->mvdd_dependency_on_mclk.entries);
mvdd_dependency_on_mclk  211 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
mvdd_dependency_on_mclk 1243 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
mvdd_dependency_on_mclk 1378 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.mvdd_dependency_on_mclk, table);
mvdd_dependency_on_mclk 1685 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
mvdd_dependency_on_mclk 1686 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
mvdd_dependency_on_mclk  271 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->dyn_state.mvdd_dependency_on_mclk);
mvdd_dependency_on_mclk  737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
mvdd_dependency_on_mclk  624 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
mvdd_dependency_on_mclk 1201 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
mvdd_dependency_on_mclk 1203 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.mvdd_dependency_on_mclk,
mvdd_dependency_on_mclk 1357 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
mvdd_dependency_on_mclk 1358 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
mvdd_dependency_on_mclk 1365 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
mvdd_dependency_on_mclk 1404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
mvdd_dependency_on_mclk 1405 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
mvdd_dependency_on_mclk 1412 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
mvdd_dependency_on_mclk 2183 drivers/gpu/drm/radeon/ci_dpm.c 						&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
mvdd_dependency_on_mclk 2314 drivers/gpu/drm/radeon/ci_dpm.c 		for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
mvdd_dependency_on_mclk 2315 drivers/gpu/drm/radeon/ci_dpm.c 			if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
mvdd_dependency_on_mclk 2321 drivers/gpu/drm/radeon/ci_dpm.c 		if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
mvdd_dependency_on_mclk 2899 drivers/gpu/drm/radeon/ci_dpm.c 	if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
mvdd_dependency_on_mclk 2901 drivers/gpu/drm/radeon/ci_dpm.c 						    &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
mvdd_dependency_on_mclk 3524 drivers/gpu/drm/radeon/ci_dpm.c 	allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
mvdd_dependency_on_mclk  958 drivers/gpu/drm/radeon/r600_dpm.c 			ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
mvdd_dependency_on_mclk 1305 drivers/gpu/drm/radeon/r600_dpm.c 	kfree(dyn_state->mvdd_dependency_on_mclk.entries);
mvdd_dependency_on_mclk 1473 drivers/gpu/drm/radeon/radeon.h 	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;