NV12              396 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SRCDST_FORMAT(NV12, rotator_s5pv210_yuv_limits) },
NV12              401 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SRCDST_FORMAT(NV12, rotator_4210_yuv_limits) },
NV12              406 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
NV12              411 drivers/gpu/drm/exynos/exynos_drm_rotator.c 	{ IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
NV12              631 drivers/gpu/drm/exynos/exynos_drm_scaler.c 	{ IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) },
NV12              694 drivers/gpu/drm/exynos/exynos_drm_scaler.c 	{ IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
NV12              412 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c 	PSEUDO_YUV_FMT(NV12,
NV12              510 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c 	PSEUDO_YUV_FMT_TILED(NV12,
NV12              115 drivers/gpu/drm/msm/disp/mdp_format.c 	FMT(NV12,     0, 8, 8, 8,  1, 2, 0, 0,  false,  true,  2, 2,