mux_uart2_p       163 drivers/clk/rockchip/clk-px30.c PNAME(mux_uart2_p)		= { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
mux_uart2_p       228 drivers/clk/rockchip/clk-px30.c 	MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       130 drivers/clk/rockchip/clk-rk3036.c PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
mux_uart2_p       156 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       152 drivers/clk/rockchip/clk-rk3128.c PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
mux_uart2_p       193 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       161 drivers/clk/rockchip/clk-rk3228.c PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
mux_uart2_p       207 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       204 drivers/clk/rockchip/clk-rk3288.c PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
mux_uart2_p       265 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       133 drivers/clk/rockchip/clk-rk3308.c PNAME(mux_uart2_p)		= { "clk_uart2_src", "dummy", "clk_uart2_frac" };
mux_uart2_p       207 drivers/clk/rockchip/clk-rk3308.c 	MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       191 drivers/clk/rockchip/clk-rk3328.c PNAME(mux_uart2_p)		= { "clk_uart2_div",
mux_uart2_p       260 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       123 drivers/clk/rockchip/clk-rk3368.c PNAME(mux_uart2_p)		= { "uart2_src", "xin24m" };
mux_uart2_p       407 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       204 drivers/clk/rockchip/clk-rk3399.c PNAME(mux_uart2_p)	= { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
mux_uart2_p       268 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
mux_uart2_p       133 drivers/clk/rockchip/clk-rv1108.c PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
mux_uart2_p       175 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,