mux_uart1_p       162 drivers/clk/rockchip/clk-px30.c PNAME(mux_uart1_p)		= { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
mux_uart1_p       224 drivers/clk/rockchip/clk-px30.c 	MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       129 drivers/clk/rockchip/clk-rk3036.c PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       152 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       151 drivers/clk/rockchip/clk-rk3128.c PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       189 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       160 drivers/clk/rockchip/clk-rk3228.c PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       203 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       203 drivers/clk/rockchip/clk-rk3288.c PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       261 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       132 drivers/clk/rockchip/clk-rk3308.c PNAME(mux_uart1_p)		= { "clk_uart1_src", "dummy", "clk_uart1_frac" };
mux_uart1_p       203 drivers/clk/rockchip/clk-rk3308.c 	MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       188 drivers/clk/rockchip/clk-rk3328.c PNAME(mux_uart1_p)		= { "clk_uart1_div",
mux_uart1_p       256 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       122 drivers/clk/rockchip/clk-rk3368.c PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       261 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       203 drivers/clk/rockchip/clk-rk3399.c PNAME(mux_uart1_p)	= { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
mux_uart1_p       264 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
mux_uart1_p       132 drivers/clk/rockchip/clk-rv1108.c PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
mux_uart1_p       171 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,