mux_uart0_p       128 drivers/clk/rockchip/clk-rk3036.c PNAME(mux_uart0_p)	= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       148 drivers/clk/rockchip/clk-rk3036.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       150 drivers/clk/rockchip/clk-rk3128.c PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       185 drivers/clk/rockchip/clk-rk3128.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       159 drivers/clk/rockchip/clk-rk3228.c PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       199 drivers/clk/rockchip/clk-rk3228.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       202 drivers/clk/rockchip/clk-rk3288.c PNAME(mux_uart0_p)	= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       257 drivers/clk/rockchip/clk-rk3288.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       131 drivers/clk/rockchip/clk-rk3308.c PNAME(mux_uart0_p)		= { "clk_uart0_src", "dummy", "clk_uart0_frac" };
mux_uart0_p       199 drivers/clk/rockchip/clk-rk3308.c 	MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       185 drivers/clk/rockchip/clk-rk3328.c PNAME(mux_uart0_p)		= { "clk_uart0_div",
mux_uart0_p       252 drivers/clk/rockchip/clk-rk3328.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       121 drivers/clk/rockchip/clk-rk3368.c PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       257 drivers/clk/rockchip/clk-rk3368.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       202 drivers/clk/rockchip/clk-rk3399.c PNAME(mux_uart0_p)	= { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
mux_uart0_p       260 drivers/clk/rockchip/clk-rk3399.c 	MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
mux_uart0_p       131 drivers/clk/rockchip/clk-rv1108.c PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
mux_uart0_p       167 drivers/clk/rockchip/clk-rv1108.c 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,