mux_sclk_cif0_p   202 drivers/clk/rockchip/clk-rk3188.c PNAME(mux_sclk_cif0_p)		= { "cif0_pre", "xin24m" };
mux_sclk_cif0_p   333 drivers/clk/rockchip/clk-rk3188.c 	MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,