mux_pllpcm_clkm   760 drivers/clk/tegra/clk-tegra20.c static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
mux_pllpcm_clkm   768 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_MUX("spi",   mux_pllpcm_clkm,   CLK_SOURCE_SPI,   43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
mux_pllpcm_clkm   769 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_MUX("xio",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   45, 0, TEGRA20_CLK_XIO),
mux_pllpcm_clkm   770 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_MUX("twc",   mux_pllpcm_clkm,   CLK_SOURCE_TWC,   16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
mux_pllpcm_clkm   771 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_MUX("ide",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   25, 0, TEGRA20_CLK_IDE),
mux_pllpcm_clkm   772 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm,   CLK_SOURCE_DVC,   47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
mux_pllpcm_clkm   773 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm,   CLK_SOURCE_I2C1,   12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
mux_pllpcm_clkm   774 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm,   CLK_SOURCE_I2C2,   54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
mux_pllpcm_clkm   775 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm,   CLK_SOURCE_I2C3,   67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
mux_pllpcm_clkm   781 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_NODIV("uarta",	mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
mux_pllpcm_clkm   782 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_NODIV("uartb",	mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
mux_pllpcm_clkm   783 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_NODIV("uartc",	mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
mux_pllpcm_clkm   784 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_NODIV("uartd",	mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
mux_pllpcm_clkm   785 drivers/clk/tegra/clk-tegra20.c 	TEGRA_INIT_DATA_NODIV("uarte",	mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
mux_pllpcm_clkm   997 drivers/clk/tegra/clk-tegra30.c static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
mux_pllpcm_clkm  1016 drivers/clk/tegra/clk-tegra30.c 	TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),