mux_pllm_pllc2_c_c3_pllp_plla  379 drivers/clk/tegra/clk-tegra-periph.c static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
mux_pllm_pllc2_c_c3_pllp_plla  629 drivers/clk/tegra/clk-tegra-periph.c 	INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
mux_pllm_pllc2_c_c3_pllp_plla  632 drivers/clk/tegra/clk-tegra-periph.c 	INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
mux_pllm_pllc2_c_c3_pllp_plla  633 drivers/clk/tegra/clk-tegra-periph.c 	INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
mux_pllm_pllc2_c_c3_pllp_plla  636 drivers/clk/tegra/clk-tegra-periph.c 	INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
mux_pllm_pllc2_c_c3_pllp_plla  640 drivers/clk/tegra/clk-tegra-periph.c 	INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
mux_pllm_pllc2_c_c3_pllp_plla  641 drivers/clk/tegra/clk-tegra-periph.c 	INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
mux_pllm_pllc2_c_c3_pllp_plla  702 drivers/clk/tegra/clk-tegra-periph.c 	MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
mux_pllm_pllc2_c_c3_pllp_plla  726 drivers/clk/tegra/clk-tegra-periph.c 	MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
mux_pllm_pllc2_c_c3_pllp_plla  880 drivers/clk/tegra/clk-tegra114.c static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
mux_pllm_pllc2_c_c3_pllp_plla 1028 drivers/clk/tegra/clk-tegra114.c 	MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),