mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0 332 drivers/clk/tegra/clk-tegra-periph.c mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = { mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0 637 drivers/clk/tegra/clk-tegra-periph.c INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),