mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm 373 drivers/clk/tegra/clk-tegra-periph.c mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = { mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm 767 drivers/clk/tegra/clk-tegra-periph.c MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),