mux_pll_src_cpll_gpll_ppll_p  134 drivers/clk/rockchip/clk-rk3399.c PNAME(mux_pll_src_cpll_gpll_ppll_p)		= { "cpll", "gpll", "ppll" };
mux_pll_src_cpll_gpll_ppll_p  980 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
mux_pll_src_cpll_gpll_ppll_p  984 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
mux_pll_src_cpll_gpll_ppll_p 1073 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_ppll_p 1091 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
mux_pll_src_cpll_gpll_ppll_p 1204 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
mux_pll_src_cpll_gpll_ppll_p 1227 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,