mux_pll_src_cpll_gpll_p  200 drivers/clk/rockchip/clk-rk3188.c PNAME(mux_pll_src_cpll_gpll_p)	= { "cpll", "gpll" };
mux_pll_src_cpll_gpll_p  285 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  290 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  312 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p  315 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  328 drivers/clk/rockchip/clk-rk3188.c 	MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  578 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  583 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  600 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  692 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  696 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  699 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  703 drivers/clk/rockchip/clk-rk3188.c 	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  191 drivers/clk/rockchip/clk-rk3288.c PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
mux_pll_src_cpll_gpll_p  354 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  367 drivers/clk/rockchip/clk-rk3288.c 	MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  480 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  496 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p  512 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  515 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  518 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  574 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  577 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  588 drivers/clk/rockchip/clk-rk3288.c 	MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  633 drivers/clk/rockchip/clk-rk3288.c 	COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p   97 drivers/clk/rockchip/clk-rk3368.c PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
mux_pll_src_cpll_gpll_p  354 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p  365 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  377 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  386 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  402 drivers/clk/rockchip/clk-rk3368.c 	MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  474 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  504 drivers/clk/rockchip/clk-rk3368.c 	MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  515 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p  533 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  536 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  539 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  579 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  583 drivers/clk/rockchip/clk-rk3368.c 	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  132 drivers/clk/rockchip/clk-rk3399.c PNAME(mux_pll_src_cpll_gpll_p)			= { "cpll", "gpll" };
mux_pll_src_cpll_gpll_p  579 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  589 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  593 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  603 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  613 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  640 drivers/clk/rockchip/clk-rk3399.c 	MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p  666 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p  882 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1127 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1266 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
mux_pll_src_cpll_gpll_p 1310 drivers/clk/rockchip/clk-rk3399.c 	MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
mux_pll_src_cpll_gpll_p 1320 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1324 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1328 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1332 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1336 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1341 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1345 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1349 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1353 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1357 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
mux_pll_src_cpll_gpll_p 1361 drivers/clk/rockchip/clk-rk3399.c 	COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,